This invention relates to testing of integrated circuits, and more specifically to a method for testing programmable logic devices using fault emulation.
Programmable logic devices exist as a well-known type of integrated circuit (IC) that may be programmed by a user to perform specified logic functions. There are different types of programmable logic devices, such as programmable logic arrays (PLAs) and complex programmable logic devices (CPLDs). One type of programmable logic devices, called the field programmable gate array (FPGA), is very popular because of a superior combination of capacity, flexibility and cost. A FPGA typically includes an array of configurable logic blocks (CLBs) surrounded by a ring of programmable input/output blocks (IOBs). The CLBs and IOBs are interconnected by a programmable interconnect switch matrix structure. The CLBs, IOBs, and interconnect structure are typically programmed by loading a stream of configuration data (bitstream) into internal configuration memory cells that define how the CLBs, IOBs, and interconnect structure are configured. The configuration data is typically organized into frames. The configuration bitstream may be read from an external memory (e.g., an external PROM). The collective states of the individual memory cells then determine the function of the FPGA.
A typical FPGA is a very complex IC device. For example, some FPGAs in the Virtex-II family, marketed by Xilinx, Inc. of San Jose, Cailf., contain several million gates. In addition, there are millions of interconnect lines. A FPGA may be unusable when some of the gates or interconnect lines malfunction (e.g., due to fabrication errors, fabrication defects, or physical failure). Thus, it is important to test the FPGA to determine if there are defects.
An important problem in testing is test evaluation (or test grading), which is the determining of the effectiveness, or quality, of a test. Test evaluation is usually done in the context of a fault model, i.e., a model representing physical defects that may cause failure (e.g., not meeting specification). A popular fault model assumes that circuit nodes can be xe2x80x9cstuckxe2x80x9d at xe2x80x9conexe2x80x9d or xe2x80x9czeroxe2x80x9d. The quality of a test is measured by the ratio between the number of faults it detects and the total number of faults in the assumed universe of the model. This ratio is referred to as the xe2x80x9cfault coverage.xe2x80x9d
In IC technology, testing is an experiment in which an IC is exercised (e.g., by applying a test vector to some or all of the inputs of the IC) and its resulting response is analyzed to ascertain whether it behaves properly. An important tool of testing is fault simulation. It consists of simulating (using a digital computer such as a workstation) a circuit in the presence of faults. By comparing the fault simulation results between a circuit with and without faults (against the same applied test vector), one can determine the effectiveness of a testing procedure. An extensive amount of research and development has been conducted in fault simulation. Some of the ideas and results are summarized in a book entitled xe2x80x9cDigital Systems Testing and Testable Design,xe2x80x9d written by Miron Abramovici, et. al., and copyrighted in 1990 by ATandT.
Fault simulation can be used as a tool to perform fault grading. Typically, it involves many hours of computer simulation time. For example, fault simulation of a small FPGA, such as a part called XCV50, a member of the Virtex family of products available from Xilinx, Inc., involves over 1,500 CPU hours of computer time on an Ultra II SparcStations. The XCV50 is a relatively small FPGA. It has about 60,000 system gates (versus over a million in the bigger FPGAs). Thus, it will be very time consuming (thereby expensive) to use fault simulation for fault grading for large FPGAs.
It should be noted that fault grading is the foundation for many other activities, such as effective diagnosis, test generation automation, etc. Thus, it is advantageous to devise an alternative method for fault grading that does not involve prolonged operations.
The present invention involves a new method to perform testing of programmable logic devices. It uses-a programmable logic device (such as a FPGA) to emulate faults, instead of using a separate computer to simulate faults. In one embodiment, a few (e.g., two or three) known good FPGAS are selected. A fault is introduced into the design of a FPGA configuration. The configuration is loaded into the FPGAS. A test vector is applied and the result is evaluated. If the result is different from that of a fault-free configuration, the fault is caught. One application of this method is to evaluate fault coverage.
One fault model that can be advantageously used in the present invention is disclosed. In this model, programmable routing matrixes are modeled with open/short faults, and pairs of lines are divided into xe2x80x9cconnectablexe2x80x9d and xe2x80x9cnon-connectable.xe2x80x9d A pair of non-connectable lines means that two lines are not supposed to be connected in a fault-free FPGA. A pair of connectable lines means that a user of the FPGA has the flexibility of programming them to be either open or connected (i.e., shorted). The possible faults in this model are: (a) two connectable lines may be permanently shorted, or permanently open, and (b) two non-connectable lines may be permanently shorted. In one embodiment, the programmable interconnection point (PIP) of a FPGA can be used as the emulation element for open and shorts. Since the control memory cell is independently programmable, the PIP can be used to emulate xe2x80x9cfaultyxe2x80x9d circuits. Turning on a PIP that is supposed to be off in a configuration emulates a xe2x80x9cshortxe2x80x9d. Turning off a PIP that is supposed to be on in a configuration emulates an xe2x80x9copenxe2x80x9d. Under assumptions that are easily met in FPGAs, emulating a short to non-connectable line means emulating the short to a known state.
The above summary of the present invention is not intended to describe each disclosed embodiment of the present invention. The figures and detailed description that follow provide additional example embodiments and aspects of the present invention.